Presently, semiconductor integrated circuit technology is developing at an astonishing rate. Much of this amazing progress has come about due to the development of extremely small elements. By means of this great reduction in size of the elements, it has become possible to integrate a greater number of elements on a single chip, and as a result, it has become possible to realize a greater number of functions. Furthermore, a high operational speed has also been achieved as a result of the reduction in size of the elements.
The range in research into ultra high speed LSI has included research into various devices, such as very small CMOS elements, BiCMOS elements, heterobipolar elements, GaAs elements, Josephson elements, and the like. However, demands for ultra LSI at room temperatures are strong, and much is expected of silicon-based technologies in future semiconductor integrated circuit technology. Furthermore, when the reduction in logical swing resulting from the reduction in power source voltage accompanying the extreme reduction in the size of the elements, and the simplification of the manufacturing process, is taken into consideration, BiCMOS elements are also incapable of meeting the demands stated above, so that CMOS elements, which have superior symmetry in circuit operation and which permit a large noise margin, are indispensable in order to guarantee system reliability.
However, when conventional CMOS elements are employed, the power consumption, that is to say, the generation of heat, increases in proportion to the clock frequency, and this causes a problem in that the thermal noise level increases, and there is also the problem of the latch-up phenomenon.
The increase in the power consumption of the circuit resulting from high speed operation is a problem which is linked to the increase of temperature within the chip and to a deterioration in reliability and operational performance. If the thermal resistance of the circuit is represented by R.sub.t (.degree. C./W) the power consumption is represented by P(W), and the increase in temperature is represented by .DELTA.T(.degree.C.), then the relationship .DELTA.T=Rt.multidot.P obtains. If .DELTA.T is set to the allowable temperature increase of the circuit, then the smaller the value of Rt, the greater the possible value of P, and the higher the speed at which operation is possible. That is to say, in high speed circuit operations, it is necessary to reduce the thermal resistance in the circuit as much as possible.
It is a commonly known fact that the power driving capacity of a MOSFET increases with decreasing size. Formula (1) below shows the current/voltage relationship in the saturation region of the MOSFET. EQU I.sub.D =(W/2L).multidot..mu..sub.c .multidot.C.sub.ox .multidot.(V.sub.G -V.sub.TH).sup.2 ( 1)
That is, EQU C.sub.ox =(.di-elect cons..sub.r .multidot..di-elect cons..sub.0)/d.sub.ox
Here,
W: gate width PA1 L: gate length PA1 .mu..sub.c : channel mobility PA1 C.sub.ox : gate insulating film capacitance per unit of surface area PA1 V.sub.G : gate voltage PA1 V.sub.TH : threshold voltage PA1 .di-elect cons..sub.r : relative dielectric constant of the gate insulating film PA1 .di-elect cons..sub.o : dielectric constant in a vacuum PA1 d.sub.ox : thickness of the gate oxide film PA1 .di-elect cons..sub.r : relative dielectric constant of the second insulating film PA1 .di-elect cons..sub.SiO2 : relative dielectric constant of the silicon oxide SiO.sub.2 film PA1 t.sub.I : thickness of the gate insulating film PA1 .di-elect cons..sub.r : relative dielectric constant of the first insulating film PA1 .di-elect cons..sub.SiO2 : relative dielectric constant of the silicon oxide film
Now, it will be assumed that the dimensions of the device are scaled down by a factor 1/.alpha. (.alpha.&gt;1). Even if gate width W and gate length L are both reduced by the factor 1/.alpha., the drain current I.sub.D which enables driving does not change. On the other hand, if the thickness d.sub.ox of the gate oxide film is reduced by the factor 1/.alpha., the gate insulating film capacitance C.sub.ox increases by a factor .alpha., and the drain current I.sub.D enabling driving increases by the factor .alpha.. Furthermore, the load capacitance driven by this transistor (the normal gate capacitance) is expressed by C.sub.ox .multidot.L.multidot.W; however, this value is reduced by the factor 1/.alpha.. Accordingly, the amount of time necessary to charge or discharge the load capacitance is shortened by the factor 1/.alpha..sup.2. In this way, as a result of the increase in the current driving capacitance of the elements and the reduction in the load capacitance accompanying a great reduction in the size of the elements, higher speeds are attained.
However, at this point the pace of development towards decreasing element size has slowed as a result of limitations in principle or limitations in manufacturing devices. For example, the planar dimensions such as gate length L and the like have reached a level of 0.2-0.5 .mu.m, which is the theoretical limit for pattern formation by means of light. Attempts have been made to form patterns with dimensions of 0.1 .mu.m or less using X rays or electron beams or the like; however, these are presently only at the development stage.
Furthermore, a SiO.sub.2 thermal oxide film of common silicon has been used as the gate insulating film; however, the thickness thereof has been reduced to 5 nm, and this is approaching a limit. That is to say, with respect to the gate insulating film, when, under current conditions, this film reaches a thickness of approximately 3 nm, current flows as a result of the direct tunneling phenomenon, and the film no longer functions as an insulating film. In other words, it could be said of the insulating film that it has in principle reached a limit and cannot be made thinner. Accordingly, an increase in the current driving capacitance resulting from a further thinning of the gate oxide film would be extremely difficult.
On the other hand, as a result of the demand for a further increase in functions per chip, the size of the chip has, in contrast to the decreasing size of the elements, become steadily larger. As a result, the length of the wiring connecting each functional block has become greater. As a result when a transistor driving such wiring is considered, as element size is reduced, the load which is to be driven becomes larger instead of smaller, and there is even greater demand for an increase in the current driving capacity of the elements.
Transistors which drive large loads as described above require extremely large current driving capacities, and as shown in Formula (1), it is necessary that the channel width W have a large value from a few tens of .mu.m to a few hundred .mu.m. In particular, it is necessary that the transistors used in the output stage to the output circuit to the external circuitry have extremely large channel widths W.
A conventional transistor structure is shown in FIG. 16. Here, (a) shows a plan view, (b) is a cross sectional line along the line A-A', and (c) shows a equivalent circuit to (a) and (b).
In the Figure, reference 1601 indicates a gate electrode formed from n.sup.+ polycrystalline silicon, references 1602 and 1603 indicate a source and a drain respectively, reference 1604 indicates a gate insulating film formed from SiO.sub.2, and reference 1605 indicates a field oxide film.
In such a transistor, as shown in FIG. 16(c), the gate electrode itself is a RC distribution constant equivalent circuit, and a limited amount of time is required for the transmission of a signal from one end 1606 of the gate to the other end 1607.
Next, in FIG. 17, an equivalent circuit diagram of the transistor is shown. When the wiring connecting the source and the ground level is long, it becomes impossible to ignore the parasitic resistance R.sub.s and the parasitic inductance L.sub.s. The voltage drop in the source wiring is determined by the sum of the product of the parasitic resistance and the current and the product of the time differentials of the current and the parasitic inductance. In particular, if the transistor is to be operated at high speed, the time differential of the current becomes large, and the parasitic inductance participates to a great extent in the voltage drop. Furthermore, similar problems with respect to the parasitic resistance and the parasitic inductance are present in the wiring connecting the power source line and the source.
In operating transistors at ultra high speeds, the parasitic resistance and the parasitic inductance of the source wiring presented great problems in increasing the scale of integration and operation at ultra high speeds of semiconductor devices.
FIG. 18 is a graph showing the relationship between the amplitude of the signal and the position thereof when a high frequency signal is applied from one end of the gate of the transistor shown in FIG. 16. As the signal is propagated through the gate electrode, the voltage amplitude thereof attenuates. In this way, if the resistance of the gate electrode becomes large, the high-frequency components are attenuated, and even if the gate width W is made large, effective use over the entire length thereof becomes impossible.
Furthermore, in FIG. 19, the attenuation of signals when propagated through wiring lengths of 1 nm, 2 nm, 3 nm, and 4 nm is shown. As shown in the Figure, when an ultra high speed signal is propagated along wiring, power consumption is caused within the silicon substrate by the electric field components in the direction of propagation of the signal, so that dramatic waveform attenuation occurs. In this manner, in conventional transistors, the waveform of high speed signals propagated along the wiring broke down, and this represented a great barrier to high speed operation.
Furthermore, an example of a formation method for an LDD structure, which is commonly employed as a counter measure to the strong electric field in the region of the drain which has been noted to be a factor in the deterioration of the device characteristics accompanying a great reduction in size in the elements, is shown in FIG. 20. Using a polysilicon gate as a mask, comparatively low concentration (for example, 1.multidot.10.sup.13 cm.sup.-2) n.sup.- ion implantation is conducted, and then a CVDSiO.sub.2 film is deposited. Thereafter, a side wall is formed by means of isotropic mode reactive ion etching, and source/drain ion implantation is conducted. In this structure, a trade off relationship existed between the effect of a reduction in the electric field in the vicinity of the drain and a reduction in the current driving capacity as a result of the parasitic resistance of the n.sup.- layer.
As described above, a transistor having a larger current driving capacity is required in order to achieve an increase in the speed and scale of integration of devices; however, if in conventional devices, for example, the gate insulating film (SiO.sub.2) was made thinner, the transistor could not be used as a result of the direct tunneling current in the insulating film. Furthermore, when transistors having a large gate width W for large current driving were employed, a limited amount of time was required to place the transistor in an on state from one end thereof to the other end, and furthermore, there was a problem in that the waveform of high speed signals propagated through the wiring broke down.
In view of the above circumstances, the present invention has as object thereof to provide a semiconductor device having a large power driving capacity and which is capable of high speed operation.